-sverilog
-systemverilogext+sv+svh+vp+VP+v+V
+incdir+$LIB_DIR/sim/bench
+incdir+$LIB_DIR/sim/bench/bfm
+incdir+$LIB_DIR/sim/bench/common
+incdir+$LIB_DIR/sim/bench/rm
+incdir+$LIB_DIR/sim/bench/stim
+incdir+$LIB_DIR/sim/bench/test
+incdir+$LIB_DIR/sim/bench/bfm/axi4
+incdir+$LIB_DIR/sim/bench/bfm/axi4l
$LIB_DIR/sim/bench/tb_top.sv
$LIB_DIR/sim/bench/tb_pkg.svh
-unit_timescale=1ns/1ps
